1. Field of the Invention
The present invention relates to a semiconductor memory device such as a synchronous DRAM (dynamic RAM).
2. Description of the Related Art
In recent years, though various memory LSIs have been proposed in order to eliminate an access gap between a microprocessor and a memory, all of the LSIs are characterized in that input and output are performed synchronously with an external clock to increase data transfer rate. There is a memory called synchronous DRAM (hereinafter referred to as `SDRAM`) among the synchronous type memories.
The SDRAM is provided with an auto-refresh and a self-refresh as a refresh mode.
FIG. 8 is a timing chart showing an auto-refresh action of a SDRAM chip. At time t5, when a row address strobe signal /RAS and a column address strobe signal /CAS are at low levels and a write enable signal /WE and a clock enable signal CKE are at high levels, the auto-refresh is actuated. At time t6, when signals similar to those at time t5 are inputted, the auto-refresh is repeated again.
In the auto-refresh a refresh address is generated in an internal refresh counter, a row of memory cells corresponding to the refresh address is refreshed, and then the row of memory cells is automatically put in a precharged state. In order to refresh all memory cells it is usually sufficient to repeat the auto-refresh 4096 times.
FIG. 9 is a timing chart showing the self-refresh action of the SDRAM chip. At time t7, after a row address strobe signal /RAS, a column address strobe signal /CAS and a clock enable signal CKE become low and a write enable signal /WE becomes high, the self-refresh is actuated while a clock enable signal CKE is at a low level.
In the self-refresh the action similar to the auto-refresh is automatically performed at constant intervals by an internal timer.
In a refresh system standardized by JEDEC, since it has been determined that a plurality of memory banks are alternately refreshed, the respective memory banks can not be refreshed simultaneously, or concurrently with a refresh action on one of the memory banks, the other of the memory banks can not be accessed. Also, a bank to be refreshed can not be designated from the banks.
As conventional technique for providing a synchronous type DRAM having a plurality of memory banks, each memory of which is accessible independently, with a function for refreshing the plurality of memory banks simultaneously, a function for allowing one or more memory banks of the plurality of memory banks to be designated for refreshing, and a function for performing memory access concurrently with refresh action and independently therewith, thereby improving memory function, there are Japanese Unexamined Patent Publications JP-A 9-139074 (1997), JP-A 7-226077 (1995), JP-A 8-77769 (1996), JP-A 7-169266 (1996), etc.
FIG. 7 shows a block diagram of a configuration example of SDRAM disclosed in Japanese Unexamined Patent Publication JP-A 9-139074 (1997) as one of the conventional techniques.
The SDRAM of the configuration example includes a memory array 200A configuring a memory bank (BANKA) and a memory array 200B configuring a memory bank (BANKB). Each of the memory arrays 200A and 200B includes dynamic type memory cells arranged in a matrix, each of the memory cells being configured with a capacitor for storing data and a MOS transistor with a gate connected to word lines (not shown) and a drain connected to complementary bit lines (not shown).
One of the word lines (not shown) in the memory array 200A is driven to a selection level according to the decode result of a row address signal generated by a row decoder 201A. The not illustrated complementary bit lines in the memory array 200A are connected to a sense amplifier and column selecting circuit 202A. The amplifier in the sense amplifier and column selecting circuit 202A is an amplifying circuit for detecting fine voltage differences appearing in respective complementary bit lines by reading data from the memory cells to amplify the fine voltage differences. The column switching circuit in the sense amplifier and column selecting circuit 202A is a switching circuit for selecting the complementary bit lines individually to connect the selected complementary bit line to a common bit line 204. The column switching circuit performs a selecting action according to a decode result of a column address signal generated by a column decoder 203A.
On the memory array 200B side, similarly, a row decoder 201B, a sense amplifier and column selecting circuit 202B and a column decoder 203B are provided.
The complementary common bit line 204 is connected to an output terminal of an input buffer 210 and an input terminal of an output buffer 211. An input terminal of the input buffer 210 and an output terminal of the output buffer 211 are connected to 8 bit data input/output terminals I/O 0 to I/O 7.
Row address signals and column address signals supplied from the address input terminals A0 to A11 are taken in a column address buffer 205 and a row address buffer 206 in address multiplex forms. The address signals supplied are held in the respective buffers. The row address buffer 206 takes in a refresh address signal output from a refresh counter 208 as a row address signal in a refresh action mode. Output of the column address buffer 205 is supplied as preset data for a column address counter 207, and the column address counter 207 outputs column address signals serving as the preset data or values produced by sequentially incrementing the output column address signals towards the column decoders 203A, 203B in accordance with an action mode specified by a command.
A control circuit 212, which is not limited, is one of a type to which external control signals such as clock signal CLK, clock enable signal CKE, chip selecting signal /CS, column address strobe signal /CAS, row address strobe signal /RAS, write enable signal /WE, data input/output mask control signal DQM (not shown), etc. and control data from the address input terminals A0 to A11 are supplied to produce internal timing signals for controlling action mode of the SDRAM and action of the circuit block based upon variations of levels, etc. of these signals. For this reason, the control circuit 212 is provided with a control logic (not shown) and a mode register 30. It is to be noted that the symbol `/` represents a low enable signal.
The clock signal CLK serves as a master clock for the SDRAM and the other external input signals are latched synchronously with a rising edge of the internal clock signal CLK. The chip selecting signal /CS instructs start of command input cycle by the low level. The respective signals /RAS, /CAS and /WE are signals different in function from corresponding signals of a normal DRAM and used when command cycle is set.
The clock enable signal CKE is a signal for indicating validity of the next clock signal, wherein it is determined that the rising edge of the next clock signal CLK is valid when the signal CKE is at a high level, while it is determined that the rising edge is invalid when the signal CKE is at a low level. Further, in a read mode not shown, an external control signal for controlling output enable on an output buffer 211 is supplied to the control circuit 212 and, when the signal is, for example, at a high level, the output buffer 211 is put in a high impedance state.
The row address signal is defined by levels of the address input terminals A01 to A10 in bank active command cycle synchronized with the rising edge of the clock signal CLK (internal clock signal). An input from the address input terminal A11 is regarded as a bank selecting signal in the bank active command cycle. That is, when the input of the terminal A11 is at a low level, the memory bank BANKA is selected and when the input is at a high level, the memory bank BANKB is selected. A selection control for the memory bank, which is not limited particularly, can be performed by such a processing as activation of only the row decoder at the selected memory bank side, all non-selection of the column switching circuit at non-selected memory bank side, connection to only the input buffer 210 and the output buffer 211 at the selected memory bank side, etc.
An input of the terminal A10 in a precharge command cycle indicates an aspect of a precharge action to the complementary bit lines or the like, wherein a high level of the input indicates that both the memory banks are subjects to be precharged and a low level of the input indicates that one memory bank indicated by the terminal A11 is a subject to be precharged.
The column address signal is defined by levels of the terminals A0 to A8 in read command or write command (column address read command and column address write command described later) cycle. The column address thus defined serves as a start address for burst access.
The SDRAM is provided with the following two refresh commands.
(1) Refresh command 1
This command is a command required for starting an auto-refresh and is indicated by /CS, /RAS, /CAS=low level, and /WE, CKE=high level. In the auto-refresh command, the two memory arrays 200A and 200B (memory banks A and B) are refreshed simultaneously in a lump.
(2) Refresh command 2
This command is a command required for starting an auto-refresh at each memory bank and is indicated in a manner different from the command 1 by, for example, /CS, /RAS, /CAS=low level, and /WE, CKE=low level. In the auto-refresh command, a specific bit in the mode register 30 is referred to. For example, when the specific bit is 0, the memory array 200A is refreshed, and when the specific bit is 1, the memory array 200B is refreshed. Besides, for example, when the signal DQM is at a low level, the memory array 200A is refreshed and when the signal DQM is at a high level, the memory array 200B is refreshed.
In FIG. 7, only address selection in the row system is performed in the refresh action. Namely, when an address signal generated from the refresh counter 208 is taken in the row address buffer 206 instead of the address signal from the external and when the refresh command 1 is inputted, selecting actions of the word lines of the memory arrays 200A and 200B and an amplifying action of the sense amplifier are performed. Namely, memory information of dynamic type memory cells connected to the selected word lines in the two memory arrays 200A and 200B is sensed and amplified to be rewritten in the original memory cells (refresh). Alternatively, when the refresh command 2 is inputted, selecting action of the word lines of one of the memory arrays 200A and 200B and an amplifying action of the sense amplifier are effected.
In the refresh command 2, for example, when a refresh action is performed on the memory array 200A (memory bank A), read/write can be conducted by another command in the other memory array 200B (memory bank B). For example, in the burst mode, the selection action for the word lines has been conducted in the memory array 200B (memory bank B) and the read/write is carried out according to the address formed by a built-in column address counter 207.
The refresh action of the plurality of memory banks in a lump and the refresh action of one or more memory banks designated of the plurality of memory banks are performed by a command specified by a combination of control signals so that the refresh actions can be made convenient in accordance with an interface of the synchronous DRAM.
A designation of the memory bank to be refreshed is performed by referring to designation information of the memory bank stored in advance in the register according to a refresh command produced by a combination of control signals so that refresh actions of various combinations can be implemented by simple configuration.
As described, when an access action such as read/write, etc. is being performed, an auto-refresh or self-refresh can be effected in another memory bank. However, the designation of the memory bank to be auto-refreshed must be conducted by setting the mode register 30. Also, the designation of the memory bank to be self-refreshed and a termination procedure of the self-refresh are not shown.